In recent years, semiconductor devices (integrated circuit devices) with a three-dimensional structure formed by stacking semiconductor chips were announced. For example, Kurino et al. announced an “Intelligent Image Sensor Chip with Three-Dimensional Structure” in 1999 IEDM Technical Digest published in 1999 (see Non-Patent Document 1).
This image sensor chip has a four-layer structure, where a processor array and an output circuit are located in the first layer, data latches and masking circuits are located in the second layer, amplifiers and analog-to-digital converters are located in the third layer, and an image sensor array is located in the fourth layer. The uppermost surface of the image sensor array is covered with a quartz glass layer containing the microlens array. The microlens array is formed on the surface of the quartz glass layer. A photodiode is formed as the semiconductor light-receiving element in each image sensor of the image sensor array.
The respective layers constituting the four-layer structure are mechanically connected to each other with an adhesive, and are electrically connected to each other with buried interconnections using conductive plugs and microbump electrodes contacted with the interconnections.
Moreover, Lee et al. announced an image-processing chip comprising image sensors similar to the solid-state image sensor announced by Kurino et al. in Japan Journal of Applied Physics entitled “Development of Three-Dimensional Integration Technology for Highly Parallel Image-processing Chip” published in April 2000 (see Non-Patent Document 2).
The image sensor chip of Lee et al. has approximately the same configuration as the solid-stage imaging sensor announced by Kurino et al. in the above-described treatise.
With any one of the two above-described semiconductor devices (integrated circuit devices) having the three-dimensional stacked structure, a plurality of semiconductor wafers are stacked and adhered to each other to form a wafer stack and thereafter, the wafer stack is divided into a plurality of chips by cutting (dicing), resulting in the semiconductor devices (integrated circuit devices). In other words, semiconductor wafers in which integrated circuits have been respectively formed are stacked and fixed on the wafer level, realizing the three-dimensional stacked structure.
By the way, recently, a microelectro-mechanical system constituted by sequentially stacking a plurality of semiconductor device chips (semiconductor chips) and/or micro electronic components on a substrate has been attracting public attention. This is because there is a possibility that semiconductor chips having different functions and/or sizes can be combined and used for this system as necessary, and because if this is realized, there is an advantage that the degree of freedom in designing is expanded.
For example, Non-Patent Document 3 discloses a self-assembly technique of microdevices to be used for a microelectro-mechanical system (MEMS). This technique is a technique to mount a plurality of micro electronic components on a single substrate by utilizing hydrophobicity and capillary force. The substrate has hydrophobic alkanethiol-coated gold binding sites. To perform assembly, hydrocarbon oil, which has been applied to the surface of the substrate, wets exclusively the hydrophobic binding sites in water. Next, micro electronic components are put into the water, and assembled respectively on the oil-wetted biding sites. Here, by using an electrochemical method to deactivate specific biding sites, the components are assembled at the biding sites by capillary forces as desired. By repeatedly conducting these steps, different batches of micro electronic components can be sequentially assembled onto the single substrate. After the assembly operation is completed, electrical connection between the substrate and the components thus assembled is established by electroplating.    Non-Patent Document 1: H. Kurino et al., “Intelligent Image Sensor Chip with Three Dimensional Structure”, 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999    Non-Patent Document 2: K. Lee et al., “Development of Three-Dimensional Integration Technology for Highly Parallel Image-processing Chip”, Jpn. J. of Appl. Phys., Vol. 39, pp. 2474-2477, April 2000    Non-Patent Document 3: X. Xiong et al., “Controlled Multibatch Self-Assembly of Microdevices”, Journal of Michroelectromechanical Systems, Vol. 12, No. 2, pp. 117-127, April 2003